Standard compliance of CPU cores is a corner point for the Risc-V eco system.

We provide tools and verification services to companies using or writing their own RISC-V cores.

Our formal verification test suite for RISC-V CPUs is used by chip design companies worldwide to achieve ISA compliance with their core implementation. As a member of the RISC-V foundation, our company is actively involved in the formal verification workgroup.

Clifford Wolf is providing an overview of how to verify your core in this talk.

You are invited to use our open source formal testbench for your CPU written in Verilog.

Authors of CPU cores using VHDL or SystemVerilog are able to use our riscv-formal testbench with our commercial Symbiotic EDA Suite.

Examples of formally verified RISC-V cores: