Enable students to design real systems — from day one.
Enable students to design real systems — from day one.
We provide a fully managed, ready-to-use design environment for teaching FPGA and ASIC design — without the complexity of installing and maintaining tools.
Our platform removes one of the biggest barriers in education: tool setup.
Whether on Windows, macOS, or Linux, students and educators can immediately start designing, simulating, and deploying — with a consistent, reproducible environment.
You focus on teaching design. We take care of the infrastructure.
mixed signal chip design
mixed signal chip design
Our Managed Design Environment BlueGarden makes it more convenient to learn how to design mixed signal chips with open source EDA tools.
You want to focus on teaching the principles of ASIC design, not spending your time maintaining a collection of software tools you have chosen as the learning environment for your students. We provide you a dependable turnkey design environment. We make sure that your tools work, all the time.
Stay on top of design files, scrips, simulation testbenches, verification results, and deliverables. Tracking who, what, when, with what tools enables fluid cooperation of students and to track down the source of problems. And if something does not work as you expect, we are here to help. Hosted by us or on premise within your compute infrastructure.
Bluegarden ASIC Design Environment
does host the following free tools:
gitlab, goCD, Yosys, Xscheme, NGspice, Xyce, Verilator, IcarusVerilog, openEMS, magic, KLayout CLI, open source PDKs from Skywater, Global Foundries, IHP,
SI-Time STA by Silicon Highway Technologies
courses making use of Bluegarden
1 day 6 hours : analog chip design intro by Dr. Juan Moya
3 days 18 hours : bootcamp analog chip design, by Dr. Juan Moya
15 weeks 30 hours : analog chip design starter, by Dr. Juan Moya
15 weeks 30 hours: advanced mixed signal chip design & tape out, by Dr. Juan Moya
15 weeks 30 hours: RF chip design, verification & tape out
trusted training partners using Bluegarden
Dr. Suren Abazyan
15 weeks 30 hours online training: RTL2GDS2 digital chip design starter
free course material
15 weeks ETH Zürich VLSI design with open source tools
15 weeks KIT Risc-V SoC ASIC design course with open source tools
10 weeks NTNU Carsten Wulf Analog Chip Design with open source tools
5 full days Thorsten Knoll digital design course with open source tools
5 full days IHP analog design course wtih open source tools
Learn UVM 8 modules
FPGA Design Environment
FPGA Design Environment
No setup. Full workflow. Immediate results.
No setup. Full workflow. Immediate results.
Our turnkey FPGA design environment provides a complete development flow — directly in the browser:
Editing, simulation, visualization, and bitstream generation
Support for multiple FPGA vendors (Gowin, Lattice, AMD)
Consistent environment for all students
No installation required
Students can:
design and simulate circuits
deploy directly to FPGA boards from their browser
Educators benefit from:
easy evaluation of student work
structured deliverables and feedback workflows
immediate onboarding from the first session
Platform Capabilities
Platform Capabilities
Web-based FPGA design, simulation, and deployment
Cloud-based bitstream compilation (CaaS platform)
CI-based design validation with:
Verilator
Yosys
nextpnr
GitLab
GoCD
Learning Resources
Learning Resources
FPGA Starter Course - 15 weeks / 30 hours
Collection of simple reference designs
Advanced RTL design & verification courses (on request)
Your productivity is our passion
Our turnkey digital design tool solution require no installation, does support FPGA from several vendors, provide a consistent and complete development flow for every student for editing, simulation, visualisation and bitstream generation.
It makes it easy for teachers to evaluate deliverables and give valuable feedback. We enable teaching assistents to educate their students from the first day of the semester.
Students can load their design into the FPGA board on their desk from the convenience of their web-browser. This demo video shows you how to use it. Its free! Try it out.
free web based FPGA design/simulation/deploy environment
educational FPGA boards from Gowin, Lattice, AMD are supported on our free to use cloud based bitstream compile platform CAAS .
free course material
15 weeks 30 hours : FPGA-starter
Bluegarden FPGA CI environment: Verilator, Yosys, nextpnr, gitlab, goCD,
courses
15 weeks 30 hours: advanced RTL design and verification (on request)
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