20 week long RTL2GDS2 training started
20 week long RTL2GDS2 training started
(July 2025) Suren did start his free starter training to become a digital chip design engineer. 20 students use the Symbiotic EDA Bluegarden Managed Design Platform to learn about synthesis, logic simulation, place&route, static timing analysis, parasitic extraction.
China deploys open source EDA tools
China deploys open source EDA tools
(June 2025) At a conference in Frankfurt/Oder members of the Chinese Academy of Science presented their chip design environment which they use to teach their next generation of chip desing engineers.
Students get to manufacture their chip in an open source 55nm technology.
For synthesis, they use the open source tool Yosys, developed by our company.
Training in Mexico
Training in Mexico
(June 2025) There will be a 4 day summerschool to learn chip design with open source EDA tools.
Mixed signal chip training in Chile
Mixed signal chip training in Chile
(June 2025) Symbiotic EDA team member Juan will give a one day IEEE training in Chile in October 2025 on how to use open source EDA tools with open source IHP PDK to design a mixed signal chip.
Where FPGA shine
Where FPGA shine
(June 2025) A thorough study evaluated the use cases of FPGAs
FPGAs are effective for AI, scientific computing, space tech, bioinformatics, data analytics, security, HPC infrastructure, and real-time systems.
They are particularly useful for tasks needing low lateny, high throughput, low power, and flexibility.
Zynq OSS tools presentation in Tokyo
Zynq OSS tools presentation in Tokyo
(June 2025) Our team member Yimin Gu gave a presentation at the Oscar Confernence about the open source FPGA tool chain for Zynq 7x0x FPGAs .
Continuous Integration for FPGA projects
Continuous Integration for FPGA projects
(June 2025) Angelo wrote a report about how he maintains the quality of his DDR3 memory controller by using the Symbiotic EDA Continuous Integration system
Linux capable 64 bit SoC
designed with Open Source EDA tools
Linux capable 64 bit SoC
designed with Open Source EDA tools
(May 2025) End-to-end open-source electronic design automation (OSEDA) enables a collaborative approach to chip design conducive to supply chain diversification and zero-trust step-by-step design verification. However, existing end-to-end OSEDA flows have mostly been demonstrated on small designs and have not yet enabled large, industry-grade chips such as Linux-capable systems-on-chip (SoCs). This work presents Basilisk, the largest end-to-end open-source SoC to date. Basilisk’s 34 mm2, 2.7 MGE design features a 64-bit Linux-capable RISC-V core, a lightweight 124 MB/s DRAM controller, and extensive IO, including a USB 1.1 host, a video output, and a fully digital 62 Mb/s chip-to-chip (C2C) link. We implement Basilisk in IHP’s open 130 nm BiCMOS technology, significantly improving on the state-of-the-art (SoA) OSEDA flow.
EU Chips Act failed to achieve its goals
EU Chips Act failed to achieve its goals
(May 2025) The evaluation of the chips act did conclude that the actions put in place by the EU commission will by far not achieve its intended goals. The worldwide markethshare of European chip will shrink from 9% down to 5% instead of achieving 20% as stated as goal by the EU Commission in 2022.
EDA innovation gap
EDA innovation gap
(January 2025) Startups in EDA face steep challenges from the oligopol of the three dominating vendors, high R&D costs, and cautious investors in a rapidly evolving semiconductor market.
German EDA conference 2024
German EDA conference 2024
(Dec 2024) We participated in the 2 day EDA Forum in Berlin, organized by the EDA-Zentrum. We presented the current status of available open source EDA tools, when they are a good choice, and when better to not use them.
Academics consider open source EDA as essential
Academics consider open source EDA as essential
(May 2024) In an open letter to the EU Commission 500 academics tried to point out how imporant open source EDA tools are for the education for the next generation of European chip design engineers.
Undergrads design chips
Undergrads design chips
(May 2024) At Cornell University, the Cornell Custom Silicon Systems (C2S2) team introduces students to microchip design and fabrication using open-source tools. This initiative breaks down the barriers of high-cost and complex technology, allowing students to design, test, and create their own microchips. Collaborations like the one with the Cornell Lab of Ornithology, where students developed a chip for recording bird vocalizations, demonstrate the practical applications of this hands-on learning. Through this project, students gain invaluable experience in semiconductor technology, fostering innovation in both education and research.
Page updated
Report abuse