Upskill opportunities in chip design
Upskill opportunities in chip design
(Oct 2025) During an IEEE workshop in Bogota, Juan Sebastian Moya from Symbiotic EDA did discuss with the panel challenges and opportunties of chip design workforce development in Latin America.
Symbiotic EDA is looking forward to collaboreate with Universidad National de Colombia, Universidad Distrital Francisco Jose de Caldas and Catholic University of Uruguay to enable chip design education.
Estonian companies and academics receive open source EDA training
Estonian companies and academics receive open source EDA training
At the recent workshop held from September 3 to 5, 2025, at TalTech – Tallinn University of Technology, Estonian companies were trained on open-source EDA tools through hands-on sessions and cutting-edge talks focused on chip design, and edge AI. Notably, sessions led by experts like Philippe Sauter, Michael Rogenmoser, and Natalia Cherezova delved into practical open-source chip design and RISC-V SoCs using the PULP platform, fostering new partnerships and bridging academia with Estonia's growing semiconductor sector.
Demo how to design a mixed signal chip end2end with open source tools
Demo how to design a mixed signal chip end2end with open source tools
(Sept 2025) Having a good example of how a mixed signal chip is done with open source tools makes it much easier for learners to make progress. Full transparency of every step and how every tool is used along the way gives students a good guidance to achieve their learning goal.
We designed ASICone using our collection of open source EDA tools within our Bluegarden design environment.
We used the 130 nm IHP open source PDK . The 2mm² 38 pin chip contains an ADC connected to a SPI core and a 10MHz oscillator.
More detailed documentation about how the design was done and verified will be added. Design elements and documentation are available from our gitlab repository.
In this video you can see the several hundred individual steps done in the IHP fab to manufacture our chip.
ETH Zürich’s chip design course shifts to Open-Source EDA tools
ETH Zürich’s chip design course shifts to Open-Source EDA tools
(September 2025) ETH Zürich’s Integrated Systems Laboratory has shifted its 2025 VLSI2 IC Design course to a mostly open-source format, using tools like Yosys, OpenRoad, and the IHP 130nm PDK. Course materials are now online at vlsi.ethz.ch. Replacing exams with project-based grading, 65 students produced 33 designs, with 28 functional and 18 tape-out ready. Five top designs will be manufactured, supported by IHP. Despite concerns about industry relevance, the course emphasizes IC design fundamentals, blending open-source and some Siemens EDA commercial tools. The move to a mature 130nm node offers hands-on learning, with plans for an advanced node follow-up course.
European Universities push for Open-Source
EDA tools to boost Chip Design Education
European Universities push for Open-Source
EDA tools to boost Chip Design Education
(August 2025) A position paper highlights the critical role of Universities in addressing Europe’s chip design capability deficit and skilled labor shortage. It emphasizes the need for open-source Electronic Design Automation (EDA) tools to enhance chip design education and research. These tools eliminate restrictive non-disclosure agreements and vendor-specific constraints, fostering collaboration, accelerating innovation, and improving design enablement. By leveraging open-source EDA tools, IP, and PDKs, Universities can simplify design flows, increase accessibility for students, and drive technological advancements, positioning Europe to strengthen its semiconductor industry competitiveness.
Symbiotic EDA offers managed solutions for the educational market to address the challenges mentioned in the position paper.
20 week long RTL2GDS2 training started
20 week long RTL2GDS2 training started
(July 2025) SOur educational partner Suren did start his free starter training to become a digital chip design engineer. 20 students use the Symbiotic EDA Bluegarden Managed Design Platform to learn about synthesis, logic simulation, place&route, static timing analysis, parasitic extraction.
China deploys open source EDA tools
China deploys open source EDA tools
(June 2025) At a conference in Frankfurt/Oder members of the Chinese Academy of Science presented their chip design environment which they use to teach their next generation of chip desing engineers.
Students get to manufacture their chip in an open source 55nm technology.
For synthesis, they use the open source tool Yosys, developed by our company.
Training in Mexico
Training in Mexico
(June 2025) There will be a 4 day summerschool to learn chip design with open source EDA tools.
Mixed signal chip training in Chile
Mixed signal chip training in Chile
(June 2025) Symbiotic EDA team member Juan will give a one day IEEE training in Chile in October 2025 on how to use open source EDA tools with open source IHP PDK to design a mixed signal chip.
Where FPGA shine
Where FPGA shine
(June 2025) A thorough study evaluated the use cases of FPGAs
FPGAs are effective for AI, scientific computing, space tech, bioinformatics, data analytics, security, HPC infrastructure, and real-time systems.
They are particularly useful for tasks needing low lateny, high throughput, low power, and flexibility.
Zynq OSS tools presentation in Tokyo
Zynq OSS tools presentation in Tokyo
(June 2025) Our team member Yimin Gu gave a presentation at the Oscar Confernence about the open source FPGA tool chain for Zynq 7x0x FPGAs .
Continuous Integration for FPGA projects
Continuous Integration for FPGA projects
(June 2025) Angelo wrote a report about how he maintains the quality of his DDR3 memory controller by using the Symbiotic EDA Continuous Integration system
Linux capable 64 bit SoC
designed with Open Source EDA tools
Linux capable 64 bit SoC
designed with Open Source EDA tools
(May 2025) End-to-end open-source electronic design automation (OSEDA) enables a collaborative approach to chip design conducive to supply chain diversification and zero-trust step-by-step design verification. However, existing end-to-end OSEDA flows have mostly been demonstrated on small designs and have not yet enabled large, industry-grade chips such as Linux-capable systems-on-chip (SoCs). This work presents Basilisk, the largest end-to-end open-source SoC to date. Basilisk’s 34 mm2, 2.7 MGE design features a 64-bit Linux-capable RISC-V core, a lightweight 124 MB/s DRAM controller, and extensive IO, including a USB 1.1 host, a video output, and a fully digital 62 Mb/s chip-to-chip (C2C) link. We implement Basilisk in IHP’s open 130 nm BiCMOS technology, significantly improving on the state-of-the-art (SoA) OSEDA flow.
EU Chips Act failed to achieve its goals
EU Chips Act failed to achieve its goals
(May 2025) The evaluation of the chips act did conclude that the actions put in place by the EU commission will by far not achieve its intended goals. The worldwide markethshare of European chip will shrink from 9% down to 5% instead of achieving 20% as stated as goal by the EU Commission in 2022.
EDA innovation gap
EDA innovation gap
(January 2025) Startups in EDA face steep challenges from the oligopol of the three dominating vendors, high R&D costs, and cautious investors in a rapidly evolving semiconductor market.
German EDA conference 2024
German EDA conference 2024
(Dec 2024) Symbiotic EDA participated in the 2 day EDA Forum in Berlin, organized by the EDA-Zentrum. We presented the current status of available open source EDA tools, when they are a good choice, and when better not to use them.
European academics consider open source EDA as essential
European academics consider open source EDA as essential
(May 2024) In an open letter to the EU Commission 500 academics tried to point out how imporant open source EDA tools are for the education for the next generation of European chip design engineers.
Undergrads design chips
Undergrads design chips
(May 2024) At Cornell University, the Cornell Custom Silicon Systems (C2S2) team introduces students to microchip design and fabrication using open-source tools. This initiative breaks down the barriers of high-cost and complex technology, allowing students to design, test, and create their own microchips. Collaborations like the one with the Cornell Lab of Ornithology, where students developed a chip for recording bird vocalizations, demonstrate the practical applications of this hands-on learning. Through this project, students gain invaluable experience in semiconductor technology, fostering innovation in both education and research.
undergrad students in Bosnia Herzegovina designed and shiped analog chips
undergrad students in Bosnia Herzegovina designed and shiped analog chips
(June 2023) Aleksandar Pajkanović and his team at the University of Banja Luka achieved a remarkable milestone by designing and fabricating the first integrated circuit (IC) ever created in Bosnia and Herzegovina, using a fully open-source EDA toolchain. Their approach—from schematic capture and simulation through layout and extraction to silicon-ready GDSII output—relied solely on free tools such as XCircuit, ngspice, Magic, and the qflow suite. This pioneering effort not only demonstrated that high-quality IC fabrication is doable without costly proprietary software, but it also laid a foundation for cybersecurity innovation and hands-on education, empowering both students and researchers in the region to participate in advanced chip design without financial barriers.
"Make chip design fun again" presentation at RISC-V conference in Tokyo
"Make chip design fun again" presentation at RISC-V conference in Tokyo
(May 2019) Symbiotic EDA’s presented it mission to make hardware design more accessible through open-source tools. Edmund Humenberger highlighted how these tools lower barriers compared to expensive proprietary software, enabling researchers, educators, startups, and hobbyists to design and prototype FPGAs and SoCs. Symbiotic EDA focuses on usability, collaboration, and teaching, aiming to accelerate development and support a growing community around open-source electronic design automation.
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