One portable tool for many FPGA architectures, with an extensible software platform that works well for small and large FPGA devices, simple 4-LUT architectures and complex ones with challenging hard-IP blocks. Our open and flexible software platform is the ideal basis for evaluating experimental FPGA architectures.

We bridge the gap between industry and academia, by providing a software platform that supports current industry FPGA architectures and at the same time has open interfaces that enable academics to develop tomorrow's P&R algorithms right on the hardware that matters in real-world applications.

The flexibility of our platform enables us to use just the right algorithm for every target device. The openness allows us to integrate improvements developed by academics and open source contributors alike, constantly improving quality of results for all users of our platform.

FPGA Synthesis with Yosys


Yosys is a framework for RTL synthesis and provides a wide range of features, such as:

  • HDL Elaboration

    • Verilog 2005 parser and elaborator

    • Support for cell libraries in different formats

  • Wide range of example architectures

    • Lattice: iCE40LP/HX/UP, ECP5
    • Xilinx: 7-Series, UltraScale, UltraScale+, Spartan-6, Coolrunner-II

    • Intel: Max10, Arria10 GX (experimental), Cyclone 10/V/IV/GX/E (experimental)

    • Basic support for Achronix, Anlogic, eASIC, Gowin, and SmartFusion2/IGLOO2

  • Powerful FPGA-mapping infrastructure

    • Logic mapping via ABC/ABC9

    • Additional functionality for mapping complex FFs (with Reset/Enable/etc.)

    • Generic infrastructure for mapping basic arithmetic

    • Generic infrastructure for mapping of DSP/MACC functions

    • Generic infrastructure for mapping (block- and distributed-) RAMs

  • Highly extensible

    • Over 150 commands for a wide range of tasks

    • Dedicated easy-to-use infrastructure for architecture exploration

    • Powerful APIs and code-generators for custom technology mapping

FPGA Synthesis with Yosys, Symbiotic EDA Suite Edition

Our Symbiotic EDA Suite contains a version of Yosys with all of the above features, plus

  • Industry-grade HDL front-ends for the following standards

    • Verilog 1995, 2000, 2005​

    • SystemVerilog 2005, 2009, 2012

    • VHDL 1987, 1993, 2000, 2008


FPGA Place&Route with nextpnr

nextpnr is a portable FPGA place-and-route tool

  • Supports a wide range of FPGA architectures in one framework

    • Production-ready support for: Lattice iCE40 and ECP5

    • Experimental architecture support: Xilinx 7-series (via torc), UltraScale+ (via rapidwright)

    • Experimental architecture support: Xilinx Spartan-3, Spartan-6, Series-7, etc (details confidential)

  • Interactive (GUI) and batch modes

    • Integrates well with console-based script/makefile-controlled build flows

    • Can also be easily launched from a custom and/or device-specific GUI front-end

    • Provides GUI for interactive use and debugging of designs, architecture, and algorithms

    • Architectures provide vector graphics for device view in a portable and easy-to-customize manner

  • Runtime-selectable place-and-route algorithms

    • Chose between SA-placer (for small devices) and analytical placer (large devices)

    • Orchestrate multiple placer/router runs using the Python API for advanced use-cases

  • Integration with other tools

    • Various netlist formats are supported, using Yosys as pre-processor

    • Some nextpnr architectures support generation of vendor-specific formats

      • This enables applications such as placement in nextpnr​ and routing in Vivado, or vice-versa​

  • Nextpnr Architecture API

    • Each nextpnr architecture back-end implements the same API

    • Using an API (common instead of file format) for architecture description

      • Greater flexibility ​for supporting architecture-specific quirks

      • Compile-time optimizations via use of inline functions

        • Architectures that don't need a functionality don't pay for their performance overhead​

      • Allow interfacing with existing proprietary ​chip databases

      • Allow use of database-type that's best suited to device size and FPGA class

    • Nextpnr algorithms (place, route) are portable and simply use this unified back-end API

  • Constraints
    • Nextpnr supports usual timing constraints (min clock period, multiple clock domains, etc)

    • Support for absolute and relative placement constraints, floorplanning

    • All nextpnr algorithms are timing-driven

    • Using architecture-independent Python API as constraint interface

    • Constraints can also be used to load partially placed and/or routed designs

    • JSON format for design check points (including all constraints and placement/routing info)

  • Python API

    • Define complex constraints via the architecture-independent nextpnr Python API

    • Use the Python API to prototype custom placement and routing algorithms

    • Or use the Python API for highly-optimized semi-automatic placement schemes

  • "generic" architecture for arbitrary custom FPGA architectures

    • Support custom architectures defined via user-supplied Python scripts

    • Enables quick architecture exploration without having to write custom back-end



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